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STE2007
96 x 68 Single-chip LCD controller/driver
Features

Low power consumption, suitable for battery operated systems Interfaces supply voltage range from 1.6 to 3.6V High voltage generator supply voltage range from 2.4 to 3.6V Display supply voltage range from 3 to 13.2V
68 x 96 bits Display Data RAM 33,49, 65 and 68 Lines mode Row by row scrolling Interfaces - 3-lines Serial Interface (read and write) - I2C (read and write) - 4-Line serial (read and write) Partial display mode (33,25,17,9 lines mode) Fully integrated oscillator that requires no external components CMOS compatible inputs Programmable ID-Number Programmable Bias Ratio Programmable columns organization Fully integrated configurable LCD bias voltage generator with: - Selectable multiplication factor (3x, 4X and 5X) - Effective sensing for high precision output - Eight selectable temperature compensation coefficients Designed for chip-on-glass (COG) applications
Description
The STE2007 is a low power LCD driver, capable to drive 96 columns and up to 68 lines, designed for monochrome displays. The STE2007 includes fully integrated bias voltage generator (up to 5x multiplication factor), and internal oscillator, thus reducing to minimum the number of external components required and the current consumption. The STE2007 features the three standard serial interfaces (3 and 4 lines serial, I2C interface).

December 2006
Rev 3
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Content
STE2007
Content
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Driver pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 CPU interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Configuration pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Test pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Display driver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 3.3 3.4 3.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MCU Tx Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Driver TxData Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 3-lines 9 bit Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1 4.1.2 MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
4-Line SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1 4.2.2
2
MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3
I C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1 4.3.2 4.3.3 4.3.4 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Starting the communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4
Reading mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4.1 IIdentification byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
Display Data RAM (DDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 DDRAM and Page/column address circuit . . . . . . . . . . . . . . . . . . . . . . . . 27
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5.2 5.3
Line address circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Partial Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3.1 5.3.2 5.3.3 5.3.4 33 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 25 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.4
Command parameters default configuration . . . . . . . . . . . . . . . . . . . . . . 38
6
Instruction setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1 6.2 6.3 Initialization (power on sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Display data writing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7 8
Power on/power off timing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 Display on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Display normal/reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Display all points on/off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Page address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Column address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Display start line address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Segment driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Common driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Display data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Data reading from driver (Driver TxData-mode) . . . . . . . . . . . . . . . . . . . 46 Power Control Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 VLCD set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.12.1 8.12.2 8.12.3 V0R - Voltage Range Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 VOP set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Electronic volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.13 8.14 8.15 8.16
Power saver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Image Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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STE2007
8.17 8.18 8.19 8.20 8.21 8.22 8.23
Bias Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Charge Pump Multiplication Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Icon mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 N- Line inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Number of lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9 10
Chip mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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Introduction
1
Introduction
In this document is specified LCD driver for Black&White full graphic displays with a resolution of 96x68, 96x65, 96x49, and 96x33 (ColumnsXRows). Abbreviations LCD COG MCU Liquid Crystal Display Chip On Glass -technology Micro Controller Unit
DDRAM Display Data Random Access Memory MSB LSB T.B.D. Table 1. Most Significant Bit Least Significant Bit To Be Defined General driver parameters
Driver assembly technology Chip On Glass (COG) Memory Size (Columns x Rows) 96x68 DDRAM capacity: 6528 bits Mux 1:68 1:65 1:49 1:33 Frame frequency (Hz) 65 70 75 80
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Introduction
STE2007
Figure 1.
Chip mechanical drawing
R66
STE2007
BUMP SIDE
(0,0) Y
X
! /
! ! 45m 72m
VSS_AUX VSS_AUX VSS_AUX VSS_AUX
R67 R65
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STE2007
Driver pin description
2
2.1
Driver pin description
CPU interface pins
Table 2.
Signal !RES !CS
CPU interface logic
Type I I Reset Input Chip Select Input When Low the communication port is enabled Must be connected to SDAIN at Module Level Description Note
SDOUT SDAIN SCLK SDA_OUT SA1 SA0
0 I I 0 I I
Serial Data Output Serial Data Input /I2C Interface Data Input Serial Clock Input/I2C Interface Clock I2C Bus Data Out I2C Slave Address I2C Slave Address
Must be left floating when I2C Interface is not is use Cannot be left floating Cannot be left floating Must be connected to VSSAUX at Module Level when 4-Line SPI is not in USE
!D/C
I
4 Line SPI Data/Command Selector
2.2
Power supply pins
Table 3.
Signal VSS VSS_LCD VSS_CP VDDI VDD VDD_CP VSSAUX
Power supply pins
Type Power Power Power Power Power Power Power Description Analog & Digital Grounds Drivers Analog Ground Booster Ground Digital Power Analog Supply Booster Power Supply Auxiliar Vss Output Note
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Driver pin description
STE2007
Table 4. Signal
VLCD
High voltage pins Type
High Voltage High Voltage High Voltage High Voltage High Voltage
Description
Booster Output Booster Sense Input LCD Row Driver Output LCD Row Driver Output LCD Column Driver Output
Note
Cext = 0.1-1F Connected to Vss Must be connected to Vlcd at module level Unused lines must be left floating Unused lines must be left floating Unused lines must be left floating
VLCD_SENSE COM0 to COM67 COMS SEG0 to SEG95
2.3
Configuration pins
Table 5. Signal
OSCIN
Configuration pin description Type
I VDDI Internal Oscillator Active
Config
VSS/VSSAUX
Description
Internal Oscillator Stopped
Note
SEL1 VSS/VSSAUX SEL0 -SEL1 I VSS/VSSAUX VDD1 VDD1
SEL0 VSS//VSSAUX VDD1 VSS/VSSAUX VDD1
Interfa I2C SPI 4-Line Serial 3-Lin Not Us
VSS/VSSAUX IDA I VDDI VSS/VSSAUX IDB I VDDI
IDA="0" IDA="1" IDB="0" IDB="1"
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Driver pin description
2.4
Test pins
Table 6. Signal
T2 T1 T0 T3 T4 T5 T6 VREF_BUFF
Test pin description Type
I I I O O O O O
Description
Test Input. Enable Test Mode. Test Input. Enable Test Mode. Test Input. Test Output. Test Output. Test Output. Test Output. Analog Test Output
Note
Must Be connected to VSS in Normal Working Mode Must Be connected to VSS in Normal Working Mode Must Be connected to VSS in Normal Working Mode Must Be OPEN in Normal Working Mode Must Be OPEN in Normal Working Mode Must Be OPEN in Normal Working Mode Must Be OPEN in Normal Working Mode Must be left floating
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Electrical characteristics
STE2007
3
3.1
Electrical characteristics
Absolute maximum ratings
Table 7.
Symbol VDDI VDD VLCD ISS Vi Iin Iout Ptot Po Tj Tstg VDD pin vs VDDI (*) All Pins(2) vs ESD maximum Withstanding Voltage range Test VDDI Condition : CDF-AEC-Q100-002-"Human body Model" Acceptance criteria: "Normal performance All Pins vs Power supplies(3)
Absolute maximum ratings
Parameter Supply Voltage Range Supply Voltage Range LCD Supply Voltage Range Supply Current Digital Inputs Voltage DC Input Current DC Output Current Total Power Dissipation (Tj = 85C) Power Dissipation per Output Operating Junction Temperature(1) Storage Temperature Value - 0.5 to + 5 - 0.5 to + 5 - 0.5 to + 14.0 - 50 to +50 -0.5 to VDDI + 0.5 - 10 to + 10 - 10 to + 10 300 30 -25 to + 85 - 65 to 150 1500 1750 Unit V V V mA V mA mA mW mW C C V V
2000
V
1. Device behavior and characterization are measured over this temperature range during internal qualification of the product. During production testing, however, device performance is measured at a fixed ambient temperature, typically 25C. 2. Except VDD pin 3. Except VDDI supply
Note:
(*) ESD tests have been performed with VSS, VSS_LCD and VSS_CP shorted together
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Electrical characteristics
3.2
DC characteristics
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 14.5 V; Tamb = 25C; unless otherwise specified.
Table 8.
Symbol VDD,VDDCP VDDI VLCD
DC characteristics
Parameter Power Supply Voltage Power Supply Voltage(Logic) Booster Output Test Condition Operating Voltage I/O supply Voltage Min. 2.4 1.6 Typ. Max. 3.6 3.6 13.5 13.5 VLCD=10V; VDD=2.6V; No display Load; fSCLK=0Hz Power Saver Mode ON (Interfaces quiescent) -2.2 2.2 Unit V V V V %
VLCD_SENSE Booster Sense Input VLCD LCD Supply Voltage Accuracy
1 6 120
5 20 250
A A A
I(VDDI)
Logic Supply Current
Power Saver Mode OFF (Interfaces quiescent) Write Mode
I(VDD +VDDCP) Logic inputs VIH VIL IIH IlL
Analog Supply Current
VLCD=10V;Booster= 5X; fSCLK=0Hz; VDD=2.4V Refresh Rate=75Hz; no display load
90
180
A
Logic High level input voltage Logic Low level input voltage Logic High level input current Logic Low level input current
0.7VDDI Vss
VDDI 0.3VDDI 1 -1
V V A A
Logic outputs VOH VOL Logic High level output voltage Logic Low level output voltage lOUT = -500A; VDDI=1.6V lOUT = 500A; VDDI=1.6V 0.8VDDI Vss VDDI 0.2VDDl V V
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Electrical characteristics
STE2007
3.3
Table 9.
Symbol FFRAME
AC characteristics
Tamb = 25C; unless otherwise specified. AC Operation - Internal oscillator
Parameter Frame Frequency Default Test condition VDDI= 1.6; VDD= 2.9V Rafresh Rate = 75Hz Min. 65 Typ. 75 Max. 84 Unit Hz
3.4
Table 10.
Symbol tcss tcsh tchw tsds
MCU Tx data mode
AC Characteristics for serial interface
Signal Description Notes Min. 60 !CS Chip select 100 50 SDAIN Input Serial Data Interface Output Serial Data interface Data setup time Data hold time Access Time SDAOUT Output Disable Time Serial clock cycle SCLK Serial clock input Serial clock H pulse width Serial clock L pulse width 100 100 0 25 250 100 100 125 100 100 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns
tsdh tac tod tscyc tshw tslw
Note:
1 2
The input signal rise and fall times must be within 10ns. Every timing is specified on the basis of 30% and 70% of VDDI.
MCU TxData timing
tchw tcss tcsh tchw
Figure 2.
!CS
tscyc tslw
SCLK
tf tsds tr tsdh
tshw
SDA/MCU TxData
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STE2007
Electrical characteristics
Table 11.
Signal Inputs
Input signals change time
Symbol tr,tf Parameter
(1)
Min.
Typ.
Max. 10
Unit ns
1. To 30% & 70% levels
3.5
Table 12.
Symbol T1 T2 T3 T4 T5
Driver TxData mode
Timings based on 4 MHz SCLK speed
Item Data hold time Access time Output disable time Data setup time !CS pulse width high Condition Note 1 - - - - Min. 100 10 25 100 250 Typ. Max. 125 100 100 - Units ns ns ns ns ns
Note:
1 2 3
Data Hold Time T1 depends on SCLK high time and Max Data Hold time. It is always 3-8ns before SCLK pulse falling edge The input signal rise and fall times must be within 10ns. Every timing is specified on the basis of 30% and 70% of VDDI.
Timings based on 1 MHz SCLK speed
Item Data hold time Access time Output disable time Data setup time 1CS pulse width high Condition - - - - - Min. 100 10 25 100 250 Typ. Max. 125 450 450 - Units ns ns ns ns ns
Table 13.
Symbol T1 T2 T3 T4 T5
Note:
1 2
The input signal rise and fall times must be within 10ns. Every timing is specified on the basis of 30% and 70% of VDDI.
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Electrical characteristics
STE2007
Figure 3.
Driver TxData Mode AC timing characteristics
Timing A SCLK
MCU TxData MCU Data direction Driver TxData
Timing B
Command Tx HiZ
T1
HiZ Rx Status
T2
Command Tx HiZ
Timing A
SCLK MCU TxData Driver TxData
Driver SDA direction in out
!CS Timing B
T3 T4
SCLK MCU TxData
D/C
Driver TxData
Driver SDA direction
out T5
in
!CS
1/2 SCLK 1/2 SCLK
3.5.1
Reset timing
Table 14.
Symbol trs trw trj
Reset timing
Signal !RES !RES !RES Reset time Reset low pulse width (for valid reset) Reset rejection (for noise spike) 2500 1000 Description Min. Max. 2500 ns Unit
Note:
1 2
The input signal rise and fall times must be within 10ns. Every timing is specified on the basis of 30% and 70% of VDDI.
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STE2007
Electrical characteristics
Figure 4.
Reset timing
trj trw
!RES trs During reset Normal operation
Internal circuit status
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Interface
STE2007
4
4.1
Interface
3-lines 9-bit serial interface
STE2007 3-lines 9 bits serial interface is a bidirectional link between the display driver and the host processor. It consists of three lines: - - - SDAIN/SDAOUT Serial Data SCLK Serial Clock !CS Peripheral enable: - Active Low- Enables and Disables the serial interface
The serial interface is active only if the !CS line is low. If !CS is low after the positive edge of !RES, the serial interface is ready to receive data after the internal reset time. Serial data must be input to SDA in the sequence D/!C, D7 to D0. STE2007 read data on SCLK rising edge. The first bit of serial data D/!C is data/command flag. When D/!C ="1" D7 to D0 bits are display RAM data or Command Parameters. When D/!C="0" D7 to D0 bits identify a command
4.1.1
MCU TxData mode (write mode)
STE2007 is always a slave device on the communication bus and receive the communication clock on the SCLK pin from the master. Information are exchanged wordwide. Every word is composed by 9 bit. The first bit is named D/!C and indicates whether the following byte is a command (D/!C =0) or a Display Data Byte (D/!C =1). During data transfer, the data line is sampled by the receiver unit on the SCLK rising edge. The data/command received is transferred to DDRAM or Executed on the first falling edge after the latching rising edge or on the !CS rising edge. If !CS stays low after the last bit of a command/data byte, the serial interface expects the D/!C bit of the next data byte on the next SCLK positive edge. A reset pulse on !RES pin interrupts any transmission. Figure 5. MCU TxData mode
!CS
SDA
D/C D7
D6
D5
D4
D3
D2
D1
D0 D/C
D7
D6
D5
D4
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
4.1.1.1 Data/command transfer break
If the Host processor generates an break condition (!CS Line HIGH before having received Bit D0) while transferring a Data byte to the Frame Memory or a Command identifier or a command parameter, the not complete received byte is discarded, the communication is interrupted and the interface is forced in reset state. When !CS line becomes low again to start a new communication session STE2007 is ready to receive the same byte interrupted re-transmitted or a new command identifier.
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STE2007
Interface
Figure 6.
3-lines SPI Data transfer break condition
Break
!CS
SCL
SDA
D7
D6
D5
D4
D3
D/!C
D7
D6
D5
D4
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0204
4.1.1.2 Data/command transfer pause
It is possible while transferring Frame Memory Data, Commands or Command Parameters to insert a pause in the data transmission (!CS Line HIGH after 8 Bits Received). When !CS is forced high after a whole byte received, the received byte is processed. Then STE2007 is forced in a wait state ready to restart processing incoming data from the point where the communication has been paused If a new command identifier is transferred after a pause condition the previous communication session is definitively closed. Four are the possible conditions: - - - - Figure 7.
!CS
Command-Pause-Command Command-Pause-Parameter Parameter-Pause-Command Parameter-Pause-Parameter
3-lines SPI data transfer pause
Pause
SCL
SDA
D3
D2
D1
D0
D/!C
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0203
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Interface
STE2007
4.1.2
Driver TxData Mode (read mode)
The Driver TxData-mode is a method to check the electrical interconnection between LCD driver and baseband, to identify the driver and for VDD Intercfonnection electrical self testing. Self Testing of the electrical contacts is based on the monitoring of VLCD. The improper electrical contact on VDD can be noted from a too low level of VLCD. The serial interface Driver TxData-mode is controlled by three input signals. The serial data output (SDAOUT/Driver TxData) and serial clock input (SCLK) are enabled when !CS is low after having received one Reading Command. To access Driver TxData-mode a Reading command must be sent to STE2007 driver. The first bit (D/C) is low to indicates next 8-bits are for command. The data is read to the driver on the rising edge of SCLK (see section "MCU TxData-mode"). After last command bit (bit 0) is read SDAOUT becomes active (Low impedance) and MCU is able to read data from driver. SDAOUT is forced in high impedence when !CS line is forced high or after the eight SCLK rising edges from the last SCLK rising edge of teh reading command transfer (Figure 8). After sending out all 8 bits the driver release automatically the bus and go back to the MCU TxData-mode. MCU Txdata line changes from high-z to active low or high in the falling edge of 8th SCLK pulse. !CS must be set high and low again before !D/C writing can continue. If !CS is forced high during the Driver TxDAta-mode, the Driver Tx data session is aborted and SDAOUT is forced in high impedance Mode. SDAOUT and SDAIN line can be short circuited in normal working conditions.
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STE2007
Interface
Figure 8.
AC timing characteristics
Timing A SCLK
MCU TxData MCU Data direction Driver TxData
Timing B
Command Tx HiZ
T1
HiZ Rx Status
T2
Command Tx HiZ
Timing A
SCLK MCU TxData Driver TxData
Driver SDA direction in out
!CS Timing B
T3 T4
SCLK MCU TxData
D/C
Driver TxData
Driver SDA direction
out T5
in
!CS
1/2 SCLK 1/2 SCLK
Figure 9.
Timing chart for start and stop of data reading from driver
Self Test command writing Reading of status
9 1 0 1 2
D/C writing
1 D/C 2 7
SCLK
1
2 7
... ... High Z ...
8
...
7
8
MCU TxData D/C='0' 0 Driver TxData
High Z ...
7 6
... ...
1
0
!CS
MCU TxData begins
Driver TxData begins
MCU TxData begins
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Interface
STE2007
4.2
4-Line SPI
STE2007 4-lines serial interface is a bidirectional link between the display driver and the host processor. It consists of four lines: - - - - SDA Serial Data SCL Serial Clock !CS Peripheral enable: - Active Low- Enables and Disables the serial interface Mode selection (D/!C).
The serial interface is active only if the !CS line is low. If !CS is low after the positive edge of !RES, the serial interface is ready to receive data after the internal reset time.
4.2.1
MCU TxData mode (write mode)
STE2007 is always a slave device on the communication bus and receive the communication clock on the SCL pin from the master. Information are exchanged byte-wide. During data transfer, the data line is sampled by the receiver unit on the SCL rising edge. D/!C line status set whether the byte is a command (D/!C =0) or a data (D/!C =1); D/!C line is read on the eighth SCL clock pulse during every byte transfer. If !CS stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next data byte on the next SCL positive edge. If !CS line is forced high in the middle of a data transfer, not complete Data bytes and Commands bytes are discarded. A reset pulse on !RES pin interrupts any transmission.
Figure 10. 4-lines SPI commands transfe
!CS D/!C SCL SDA (input) SDA (output) Hi-Z
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D0
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND
COMMAND
COMMAND
COMMAND
LR0189
Figure 11. 4-lines SPI Video data write cycle
!CS D/!C SCL SDA (input) SDA (output) Hi-Z
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D0
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND
DATA to VIDEO RAM
DATA to VIDEO RAM
DATA to VIDEO RAM
LR0190
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STE2007
Interface
4.2.1.1 Data/command transfer break
If the Host processor generates an break condition (!CS Line HIGH before having received Bit D0) while transferring a Data byte to the Frame Memory or a Command identifier or a command parameter, the not complete received byte is discarded, the communication is interrupted and the interface is forced in reset state. When !CS line becomes low again to start a new communication session STE2007 is ready to receive the same byte interrupted re-transmitted or a new command identifier. Figure 12. 4-lines SPI Data Transfer break condition
Break !CS
D/!C
SCL
SDA
D7
D6
D5
D4
D3
D7
D6
D5
D4
D3
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0192
4.2.1.2 Data/command transfer pause
It is possible while transferring Frame Memory Data, Commands or Command Parameters to insert a pause in the data transmission (!CS Line HIGH after 8 Bits Received). When !CS is forced high after a whole byte received, the received byte is processed. Then STE2007 is forced in a wait state ready to restart processing incoming data from the point where the communication has been paused If a new command identifier is transferred after a pause condition the previous communication session is definitively closed. Four are the possible conditions: - - - - Command-Pause-Command Command-Pause-Parameter Parameter-Pause-Command Parameter-Pause-Parameter
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Interface
STE2007
Figure 13. 4-lines SPI Data transfer pause
Pause !CS
D/!C
SCL
SDA
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND/PARAMETER
COMMAND/PARAMETER
LR0191
4.2.2
Driver TxData Mode (read mode)
Throughout SDA line is possible to read some registers value (ID Numbers, Status byte, temperature). SDA (output Driver) is in High impedance in steady state and during data write.
Figure 14. 4-lines SPI 8-Bit read cycle
Read Command
!CS D!C SCL
DATA
Next Command
SDA (Input) SDA (Output)
D7
D6
D5
D4
D3
D2
D1
D0 D7 D6 D5
High Z
D4 D3 D2 D1 D0
D7
D6
D5
D4
D3
D2
D1
D0
High Z
LR0255
MCU Data Tx Start LCD Driver Data Tx Start MCU Data Tx Start
4.3
I2C Bus
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast (400kHz Clock) and High Speed Mode (3.4MHz). This bus is intended for communication between different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via an active or passive pull-up. The following protocol has been defined: - - Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop Data Transfer condition (see below).
Accordingly, the following bus conditions have been defined: BUS not busy: Both data and clock lines remain High.
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STE2007
Interface
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, define the START condition. Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High, defines the STOP condition. Data Valid: The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer starts with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and the stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with the ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves" Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition. Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2007 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. To be compliant with the I2C-bus Hs-mode specification the STE2007 is able to detect the special sequence "S00001xxx". After this sequence no acknowledge pulse is generated. Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode without detecting the master code.
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Interface
STE2007
Figure 15. Bit transfer and START,STOP conditions definition
DATA LINE STABLE DATA VALID CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
D00IN1151
STOP CONDITION
Figure 16. Acknowledgment on the I2C-bus
START SCLK FROM MASTER CLOCK PULSE FOR ACKNOWLEDGEMENT 1 2 8 9
DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER
MSB
LSB
D00IN1152
4.3.1
Communication protocol
The STE2007 is an I2C slave. The access to the device is bi-directional since data write and status read are allowed. Four are the device addresses available for the device. All have in common the first 5 bits (01111). The two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs to a logic 0 or to a logic 1.
4.3.2
Starting the communication
To start the communication between the bus master and the slave LCD driver, the master must initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA bus line (Most significant bit first). This consists of the 7-bit Device Address Code, and the 1bit Read/Write Designator (R/W). The R/W bit has to be set to logic 1 to logic 0 according to the type of communication (read or write). All slaves with the corresponding address acknowledge in parallel, all the others ignore the I2C-bus transfer. Figure 17. Addree byte
STE2007 SLAVE ADDRESS SSR 01111AA / 1 0W READ or WRITE DESIGNATOR
ADDRESS BYTE
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STE2007
Interface
4.3.3
MCU TxData Mode (Write Mode)
If the R/W bit is set to logic 0 the STE2007 is set to be a receiver and the master can send commands or data. After the communication has started and slaves have acknowledged, the master sends a control byte defined as follows and waits for its acknowledgement:
CONTROL BYTE
Co DC 0 0 0 0 0 0
The Co bit is the control byte MSB and defines if after this control byte will follow a single byte sequence (Co = 1) or a multiple bytes sequence (Co = 0). The D/C bit defines whether the following byte (if Co = 1) or the following stream of bytes (if Co = 0) are command (D/C = 0) or DDRAM data (D/C = 1). Depending on state of flags Co and D/C, four writing sequences are possible: SINGLE COMMAND BYTE SEQUENCE (Co = 1, D/C = 0): a single byte interpreted as a command will follow the control byte; SINGLE DATA BYTE SEQUENCE (Co = 1, D/C = 1): a single byte interpreted as a data to be written in DDRAM will follow the control byte; MULTIPLE COMMAND BYTES SEQUENCE (Co = 0, D/C = 0): a stream of bytes will follow the control byte, with each single byte interpreted as a command; MULTIPLE DATA BYTES SEQUENCE (Co = 0, D/C = 1): a stream of bytes will follow the control byte, with each byte interpreted as a data byte to be written in DDRAM. Every single byte of a sequence must be acknowledged by all addressed units. A multiple data sequence is terminated only by sending a STOP condition on the I2C bus. When a sequence is terminated, another sequence of any type can follow or a I2C STOP condition can be sent to close the communication. In a single or multiple data bytes sequence, every data byte received is stored in the DDRAM at the location specified by the current values of data pointers. Data pointers are automatically updated after each single data byte written.
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Interface
STE2007
4.3.4
Driver TxData mode (Read mode)
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit during the last write access, is set to a logic 0, the byte read is the status byte. Figure 18. Communication protocol
WRITE MODE
COMMUNICATION START
I2C START 0 COND 1 1 1 1
STE2007 ACK
SA1 SA2
0
A
SLAVE ADDRESS
R/W
Co D/C
STE2007 ACK
STE2007 ACK
SINGLE COMMAND SEQUENCE
10000000A
COMMAND Byte
A
Control Byte Co D/C
Command Byte STE2007 ACK STE2007 ACK
STE2007 ACK
MULTIPLE COMMAND SEQUENCE
00000000A
COMMAND Byte
A
COMMAND Byte
A
Control Byte
First Command Byte
Last Command Byte
Co D/C
STE2007 ACK
STE2007 ACK
SINGLE DATA SEQUENCE
11000 000A
DATA Byte
A
Control Byte
Data Byte
Co D/C
STE2007 ACK
STE2007 ACK
STE2007 ACK
MULTIPLE DATA SEQUENCE
01000000A
DATA Byte
A
DATA Byte
A
Control Byte
First Data Byte
Last Data Byte
COMMUNICATION STOP
I2C STOP COND
READ MODE
STE2007 ACK MASTER ACK
STATUS BYTE READ SEQUENCE
I2C START 0 COND
1
1
1
1
SA1 SA2
0A
STATUS Byte
A
I2C START COND
R/W SLAVE ADDRESS
LR0008d
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STE2007
Interface
4.4
Reading mode
STE2007 features a reading Command to transmitt data from the LCD driver to Host Processor. After the reading command STE2007 transfers 8 bits to the Host controller: - Identification Byte (Command Code DBhex)
4.4.1
IIdentification byte
Identification byte is an 8 Bit code that identify the module revision Number. Table 15.
Bit nr
ID byte format
D7(MSB) 0 D6 0 D5 IDB PAD D4 IDA PAD D3 0 D2 0 D1 0 D0(LSB) 0
Figure 19. Identification byte in reading mode
STE2007
Power IC VDDCP VDD VDDI VSS VSSCP
VDD VDDI GND
Command decoder
ASIC(MCU)
MCU TxData
RESET
8 bit register
SDA XCS SCLK
Driver TxData
Multi plexer
ID
test
Auto return
VLCD
Voltage booster BaseBand side Driver side
LCD Power Supply circuit
Figure 20. Identification information
Identification Information
Send rading command (DBh)
Read status(ID data) Send reset command
Command:E2H
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Display Data RAM (DDRAM)
STE2007
5
5.1
Display Data RAM (DDRAM)
DDRAM and Page/column address circuit
The DDRAM stores pixel data for LCD. It is a 68-row (8 page by 8 bits +4) by 96-column addressable array. D7 to D0 display data from MCU corresponds to the LCD common direction. "0" bit in DDRAM is a OFF-dot on display and "1" bit in DDRAM is displayed as ON-dot on display. Figure 21. DDRAM vs. display on LCD
D0 D1 D2 D3 D4 0 1 0 0 1 11 00 00 01 10 1 0 0 1 0 1 0 1 0 1 COM0 COM1 COM2 COM3 COM4 DDRAM Display on LCD
Each pixel can be selected when page address and column address are specified. The MCU issues Page address set command to change the page and access to another page. In DDRAM page address 8 (D3,D2,D1,D0=1,0,0,0) only display data D0,D1,D2 & D3 are valid. The DDRAM column address is specified by Column address set command. The specified column address is automatically incremented by +1 when a Display data write command is entered. After the last column address (5Fh), column address returns to 00h and page address incremented by +1. After the very last address (column=5Fh, page=8h), both column address and page address return to 00h (column address=00h, page address=0h). Figure 22. Column address in normal mode
Data LSBit D0 D1 D2 D3 D4 D5 D6 MSBit D7 Data for page address 0H to 07H
0H 1H 2H 3H Page address 4H 5H 6H 7H 8H D0 D1 D2 D3
0 96 192 288 384 480 576 672 768 00H
1 97 193 289 385 481 577 673 769 01H
2 98 194 290 386 482 578 674 770 02H Column address
94 190 286 382 478 574 670 766 862 5EH
95 191 287 383 479 575 671 767 863 5FH
Data for page address 8H
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STE2007
Display Data RAM (DDRAM)
Figure 23. Column address in reversed mode
Data for page address 0H to 07H Data D0 LSBit D1 D2 D3 D4 D5 D6 D7 MSBit Page address
95
191 287 383 479 575 671 767 863
94
190 286 382 478 574 670 766 862 Column address 98 194 290 386 482 578 674 770 97 193 289 385 481 577 673 769
0H 96 1H 192 2H 288 3H 384 4H 480 5H 576 6H 672 7H 768 8H
5FH 5EH
02H 01H 00H D0 D1 D2 D3
Data for page address 8H
Data can be written to the DDRAM at the same time as data is being displayed, without causing the LCD to flicker. Segment driver direction command can be used to reverse the relationship between the DDRAM column address and segment output. This function is achieved writing data into DDRAM in reverse order (from Right to left). Table 16.
Column address Normal Direction Reverse Direction
Column address direction
00H SEG0 SEG95 01H SEG1 SEG94 02H SEG2 SEG93 5DH ______ ______ 5EH SEG93 SEG2 5FH SEG94 SEG1 5DH SEG95 SEG0
5.2
Line address circuit
The line address circuit specifies the line address relating to the COM output when the contents of the DDRAM are displayed. The display start line that is normally the top line of the display, can be specified by Display start line address set command. STE2007 features Four different Multiplexing Mode to fine tune the duty ratio on the display size: - - - - 68 Lines Display 65 Lines Display 49 Lines Display 33 Lines Display
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Display Data RAM (DDRAM)
STE2007
Figure 24. M68-line mode
ICONMODE="1"
Page address D3 D2 D1 D0 D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM66 COM0 COM65 COM1 COM64 COM2 COM3 COM63 COM4 COM62 COM5 COM61 COM6 COM60 COM7 COM59 COM8 COM58 COM9 COM57 COM10 COM56 COM11 COM55 COM12 COM54 COM13 COM53 COM14 COM52 COM15 COM51 COM16 COM50 COM17 COM49 COM18 COM48 COM19 COM47 COM20 COM46 COM21 COM45 COM22 COM44 COM23 COM43 COM24 COM42 COM25 COM41 COM26 COM40 COM27 COM39 COM28 COM38 COM29 COM37 COM30 COM36 COM31 COM35 COM32 COM34 COM33 COM33 COM34 COM32 COM35 COM31 COM36 COM30 COM37 COM29 COM38 COM28 COM39 COM27 COM40 COM26 COM41 COM25 COM42 COM24 COM43 COM23 COM44 COM22 COM45 COM21 COM46 COM20 COM47 COM19 COM48 COM18 COM49 COM17 COM50 COM16 COM51 COM15 COM52 COM14 1 COM53 COM13 COM54 COM12 COM55 COM1 COM56 COM10 COM57 COM9 COM58 COM8 COM59 COM7 COM60 COM6 COM61 COM5 COM62 COM4 COM63 COM3 COM64 COM2 COM65 COM1 COM66 COM0 COMS COMS Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM0 COMS COM66 COM1 COM65 COM2 COM3 COM64 COM4 COM63 COM5 COM62 COM6 COM61 COM7 COM60 COM8 COM59 COM9 COM58 COM10 COM57 COM11 COM56 COM12 COM55 COM13 COM54 COM14 COM53 COM15 COM52 COM16 COM51 COM17 COM50 COM18 COM49 COM19 COM48 COM20 COM47 COM21 COM46 COM22 COM45 COM23 COM44 COM24 COM43 COM25 COM42 COM26 COM41 COM27 COM40 COM28 COM39 COM29 COM38 COM30 COM37 COM31 COM36 COM32 COM35 COM33 COM34 COM34 COM33 COM35 COM32 COM36 COM31 COM37 COM30 COM38 COM29 COM39 COM28 COM40 COM27 COM41 COM26 COM42 COM25 COM43 COM24 COM44 COM23 COM45 COM22 COM46 COM21 COM47 COM20 COM48 COM19 COM49 COM18 COM50 COM17 COM51 COM16 COM52 COM15 COM53 COM14 COM54 COM13 COM55 COM12 COM56 COM11 COM57 COM10 COM58 COM9 COM59 COM8 COM60 COM7 COM61 COM6 COM62 COM5 COM63 COM4 COM64 COM3 COM65 COM2 COM66 COM1 COM0 COMS
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Start
Start
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1
0
0
0
Page 8 59H 5AH 5BH 5CH 5DH 5EH 5FH
Column address
Display start line does not access 65th, 66th, 67th, 68th line
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
Normal Direction Reverse Direction
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
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STE2007
Display Data RAM (DDRAM)
Figure 25. 65-line mode
ICONMODE="1"
D a t D3 D2 D1 D0 a Page address D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM0 COM63 COM1 COM62 COM2 COM61 COM3 COM60 COM4 COM59 COM5 COM58 COM6 COM57 COM7 COM56 COM8 COM55 COM9 COM54 COM10 COM53 COM11 COM52 COM12 COM51 COM13 COM50 COM14 COM49 COM15 COM48 COM16 COM47 COM17 COM46 COM18 COM45 COM19 COM44 COM20 COM43 COM21 COM42 COM22 COM41 COM23 COM40 COM24 COM39 COM25 COM38 COM26 COM37 COM27 COM36 COM28 COM35 COM29 COM34 COM30 COM33 COM31 COM32 COM32 COM31 COM33 COM30 COM34 COM29 COM35 COM28 COM36 COM27 COM37 COM26 COM38 COM25 COM39 COM24 COM40 COM23 COM41 COM22 COM42 COM21 COM43 COM20 COM44 COM19 COM45 COM18 COM46 COM17 COM47 COM16 COM48 COM15 COM49 COM14 COM50 COM13 COM51 COM12 COM52 COM11 COM53 COM10 COM54 COM9 COM55 COM8 COM56 COM7 COM57 COM6 COM58 COM5 COM59 COM4 COM60 COM3 COM61 COM2 COM62 COM1 COM63 COM0 COM64 COM64 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM64 COM0 COM1 COM63 COM2 COM62 COM3 COM61 COM4 COM60 COM5 COM59 COM6 COM58 COM7 COM57 COM8 COM56 COM9 COM55 COM10 COM54 COM11 COM53 COM12 COM52 COM13 COM51 COM14 COM50 COM15 COM49 COM16 COM48 COM17 COM47 COM18 COM46 COM19 COM45 COM20 COM44 COM21 COM43 COM22 COM42 COM23 COM41 COM24 COM40 COM25 COM39 COM26 COM38 COM27 COM37 COM28 COM36 COM29 COM35 COM30 COM34 COM31 COM33 COM32 COM32 COM33 COM31 COM34 COM30 COM35 COM29 COM36 COM28 COM37 COM27 COM38 COM26 COM39 COM25 COM40 COM24 COM41 COM23 COM42 COM22 COM43 COM21 COM44 COM20 COM45 COM19 COM46 COM18 COM47 COM17 COM48 COM16 COM49 COM15 COM50 COM14 COM51 COM13 COM52 COM12 COM53 COM11 COM54 COM10 COM55 COM9 COM56 COM8 COM57 COM7 COM58 COM6 COM59 COM5 COM60 COM4 COM61 COM3 COM62 COM2 COM63 COM1 COM64 COM0
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Start
Start
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1
0
0
0
Page 8 59H 5AH 5BH 5CH 5DH 5EH 5FH
Column address
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
Normal Direction Reverse Direction
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
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Display Data RAM (DDRAM)
STE2007
Figure 26. 49-line mode
ICONMODE="1"
D a t D3 D2 D1 D0 a Page address D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM0 COM47 COM1 COM46 COM2 COM45 COM3 COM44 COM4 COM43 COM5 COM42 COM6 COM41 COM7 COM40 COM8 COM39 COM9 COM38 COM10 COM37 COM11 COM36 COM12 COM35 COM13 COM34 COM14 COM33 COM15 COM32 COM16 COM31 COM17 COM30 COM18 COM29 COM19 COM28 COM20 COM27 COM21 COM26 COM22 COM25 COM23 COM24 COM24 COM23 COM25 COM22 COM26 COM21 COM27 COM20 COM28 COM19 COM29 COM18 COM30 COM17 COM31 COM16 COM32 COM15 COM33 COM14 COM34 COM13 COM35 COM12 COM36 COM11 COM37 COM10 COM38 COM9 COM39 COM8 COM40 COM7 COM41 COM6 COM42 COM5 COM43 COM4 COM44 COM3 COM45 COM2 COM46 COM1 COM47 COM0 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM0 COM48 COM47 COM1 COM46 COM2 COM45 COM3 COM44 COM4 COM43 COM5 COM42 COM6 COM41 COM7 COM40 COM8 COM39 COM9 COM10 COM38 COM11 COM37 COM12 COM36 COM13 COM35 COM14 COM34 COM15 COM33 COM16 COM32 COM17 COM31 COM18 COM30 COM19 COM29 COM20 COM28 COM21 COM27 COM22 COM26 COM23 COM25 COM24 COM24 COM25 COM23 COM26 COM22 COM27 COM21 COM28 COM20 COM29 COM19 COM30 COM18 COM31 COM17 COM32 COM16 COM33 COM15 COM34 COM14 COM35 COM13 COM36 COM12 COM37 COM11 COM38 COM10 COM39 COM9 COM40 COM8 COM41 COM7 COM42 COM6 COM43 COM5 COM44 COM4 COM45 COM3 COM46 COM2 COM47 COM1 COM48 COM0
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Start
Start
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
COM64
COM64
1
0
0
0
Page 8 59H 5AH 5BH 5CH 5DH 5EH 5FH
Column address
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
Normal Direction Reverse Direction
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
32/62
STE2007
Display Data RAM (DDRAM)
Figure 27. 33-line mode
ICONMODE="1"
D a t D3 D2 D1 D0 a Page address D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM16 COM15 COM17 COM14 COM18 COM13 COM19 COM12 COM20 COM11 COM21 COM10 COM22 COM9 COM23 COM8 COM24 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM32 COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM10 COM22 COM11 COM21 COM12 COM20 COM13 COM19 COM14 COM18 COM15 COM17 COM16 COM16 COM17 COM15 COM18 COM14 COM19 COM13 COM20 COM12 COM21 COM11 COM22 COM10 COM23 COM9 COM24 COM8 COM25 COM7 COM26 COM6 COM27 COM5 COM28 COM4 COM29 COM3 COM30 COM2 COM31 COM1 COM32 COM0
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Start
Start
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
Page 7
0
1
1
1
COM64
COM64
1
0
0
0
Page 8 59H 5AH 5BH 5CH 5DH 5EH 5FH
Column address
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
Normal Direction Reverse Direction
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
5.3
Partial display
STE2007 feature four configuration for Partial Display function: - - - - 33 Line Partial Display 25 Line Partial display 16 Line Partial Display 9 Line Partial Display
Partial display Area location on the screen is defined by Image Location Parameter. Image Location + Partial display area > Multiplexing rate.
33/62
Display Data RAM (DDRAM)
STE2007
Figure 28. Illustration of partial display
Display
Display
Image Location + Partial display area width <= Multiplexing Location + Partial display area width Image rate
>
When Partial Display Mode is enabled the user has to Update the Operative Voltage, Bias Ratio and Charge Pump Setting to match the new working conditions.
5.3.1
33 Line partial display mode
Partial Display Area is composed of 33 Lines. Memory vs. Row Drivers Mapping is defined according to the following parameters: - - Multiplexing Value IL[2:0]
Figure 29. Example: Partial display 33 lines & MUX65
ICONMODE="1"
D a t D3 D2 D1 D0 a Page address D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM0 COM63 COM1 COM62 COM2 COM61 COM3 COM60 COM4 COM59 COM5 COM58 COM6 COM57 COM7 COM56 COM8 COM55 COM9 COM54 COM10 COM53 COM11 COM52 COM12 COM51 COM13 COM50 COM14 COM49 COM15 COM48 COM16 COM47 COM17 COM46 COM18 COM45 COM19 COM44 COM20 COM43 COM21 COM42 COM22 COM41 COM23 COM40 COM24 COM39 COM25 COM38 COM26 COM37 COM27 COM36 COM28 COM35 COM29 COM34 COM30 COM33 COM31 COM32 COM32 COM31 COM33 COM30 COM34 COM29 COM35 COM28 COM36 COM27 COM37 COM26 COM38 COM25 COM39 COM24 COM40 COM23 COM41 COM22 COM42 COM21 COM43 COM20 COM44 COM19 COM45 COM18 COM46 COM17 COM47 COM16 COM48 COM15 COM49 COM14 COM50 COM13 COM51 COM12 COM52 COM11 COM53 COM10 COM54 COM9 COM55 COM8 COM56 COM7 COM57 COM6 COM58 COM5 COM59 COM4 COM60 COM3 COM61 COM2 COM62 COM1 COM63 COM0 COMS0 COMS0 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COMS0 COM0 COM1 COM63 COM2 COM62 COM3 COM61 COM4 COM60 COM5 COM59 COM6 COM58 COM7 COM57 COM8 COM56 COM9 COM55 COM10 COM54 COM11 COM53 COM12 COM52 COM13 COM51 COM14 COM50 COM15 COM49 COM16 COM48 COM17 COM47 COM18 COM46 COM19 COM45 COM20 COM44 COM21 COM43 COM22 COM42 COM23 COM41 COM24 COM40 COM25 COM39 COM26 COM38 COM27 COM37 COM28 COM36 COM29 COM35 COM30 COM34 COM31 COM33 COM32 COM32 COM33 COM31 COM34 COM30 COM35 COM29 COM36 COM28 COM37 COM27 COM38 COM26 COM39 COM25 COM40 COM24 COM41 COM23 COM42 COM22 COM43 COM21 COM44 COM20 COM45 COM19 COM46 COM18 COM47 COM17 COM48 COM16 COM49 COM15 COM50 COM14 COM51 COM13 COM52 COM12 COM53 COM11 COM54 COM10 COM55 COM9 COM56 COM8 COM57 COM7 COM58 COM6 COM59 COM5 COM60 COM4 COM61 COM3 COM62 COM2 COM63 COM1 COMS0 COM0
0
0
0
0
Page 0
IL[2:0]
IL[2:0]
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Start
Start
Partial Display Area (32 +1)
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1
0
0
0
Page 8 59H 5AH 5BH 5CH 5DH 5EH 5FH
Column address
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
Normal Direction Reverse Direction
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
34/62
Partial Display Area (33)
STE2007
Display Data RAM (DDRAM)
Figure 30. Example: Partial Display 33 lines & MUX68
ICONMODE="1"
ICONMODE="0"
Page address D3 D2 D1 D0
D a t a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
0
0
0
0
Page 0
IL[2:0]
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Start
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1
0
0
0
Page 8 59H 5AH 5BH 5CH 5DH 5EH 5FH
COM Output Normal Reverse direction direction COM66 COM0 COM65 COM1 COM64 COM2 COM3 COM63 COM4 COM62 COM5 COM61 COM6 COM60 COM7 COM59 COM8 COM58 COM9 COM57 COM10 COM56 COM11 COM55 COM12 COM54 COM13 COM53 COM14 COM52 COM15 COM51 COM16 COM50 COM17 COM49 COM18 COM48 COM19 COM47 COM20 COM46 COM21 COM45 COM22 COM44 COM23 COM43 COM24 COM42 COM25 COM41 COM26 COM40 COM27 COM39 COM28 COM38 COM29 COM37 COM30 COM36 COM31 COM35 COM32 COM34 COM33 COM33 COM34 COM32 COM35 COM31 COM36 COM30 COM37 COM29 COM38 COM28 COM39 COM27 COM40 COM26 COM41 COM25 COM42 COM24 COM43 COM23 COM44 COM22 COM45 COM21 COM46 COM20 COM47 COM19 COM48 COM18 COM49 COM17 COM50 COM16 COM51 COM15 1 COM52 COM14 COM53 COM13 COM54 COM12 COM55 COM1 COM56 COM10 COM57 COM9 COM58 COM8 COM59 COM7 COM60 COM6 COM61 COM5 COM62 COM4 COM63 COM3 COM64 COM2 COM65 COM1 COM66 COM0 COMS COMS
Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
IL[2:0]
Start
COM Output Normal Reverse direction direction COM0 COMS COM66 COM1 COM65 COM2 COM3 COM64 COM4 COM63 COM5 COM62 COM6 COM61 COM7 COM60 COM8 COM59 COM9 COM58 COM10 COM57 COM11 COM56 COM12 COM55 COM13 COM54 COM14 COM53 COM15 COM52 COM16 COM51 COM17 COM50 COM18 COM49 COM19 COM48 COM20 COM47 COM21 COM46 COM22 COM45 COM23 COM44 COM24 COM43 COM25 COM42 COM26 COM41 COM27 COM40 COM28 COM39 COM29 COM38 COM30 COM37 COM31 COM36 COM32 COM35 COM33 COM34 COM34 COM33 COM35 COM32 COM36 COM31 COM37 COM30 COM38 COM29 COM39 COM28 COM40 COM27 COM41 COM26 COM42 COM25 COM43 COM24 COM44 COM23 COM45 COM22 COM46 COM21 COM47 COM20 COM48 COM19 COM49 COM18 COM50 COM17 COM51 COM16 COM52 COM15 COM53 COM14 COM54 COM13 COM55 COM12 COM56 COM11 COM57 COM10 COM58 COM9 COM59 COM8 COM60 COM7 COM61 COM6 COM62 COM5 COM63 COM4 COM64 COM3 COM65 COM2 COM66 COM1 COM0 COMS
Partial Display Area (32 +1)
Column address
Display start line does not access 65th, 66th, 67th, 68th line
SEG Output
Normal Direction Reverse Direction
S E G 0 S E G 95
S E G 1 S E G 94
S E G 2 S E G 93
S E G 3 S E G 92
S E G 4 S E G 91
S E G 5 S E G 90
S E G 6 S E G 89
S E G 89 S E G 6
S E G 90 S E G 5
S E G 91 S E G 4
S E G 92 S E G 3
S E G 93 S E G 2
S E G 94 S E G 1
S E G 95 S E G 0
Partial Display Area (33)
35/62
Display Data RAM (DDRAM)
STE2007
5.3.2
25 Line partial display mode
Partial Display Area is composed of 25 Lines. Memory vs. Row Drivers Mapping is defined according to the following parameters: - - Multiplexing Value IL[2:0]
Figure 31. Example: Partial display 25 lines & MUX65
ICONMODE="1"
D a t D3 D2 D1 D0 a Page address D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM0 COM63 COM1 COM62 COM2 COM61 COM3 COM60 COM4 COM59 COM5 COM58 COM6 COM57 COM7 COM56 COM8 COM55 COM9 COM54 COM10 COM53 COM11 COM52 COM12 COM51 COM13 COM50 COM14 COM49 COM15 COM48 COM16 COM47 COM17 COM46 COM18 COM45 COM19 COM44 COM20 COM43 COM21 COM42 COM22 COM41 COM23 COM40 COM24 COM39 COM25 COM38 COM26 COM37 COM27 COM36 COM28 COM35 COM29 COM34 COM30 COM33 COM31 COM32 COM32 COM31 COM33 COM30 COM34 COM29 COM35 COM28 COM36 COM27 COM37 COM26 COM38 COM25 COM39 COM24 COM40 COM23 COM41 COM22 COM42 COM21 COM43 COM20 COM44 COM19 COM45 COM18 COM46 COM17 COM47 COM16 COM48 COM15 COM49 COM14 COM50 COM13 COM51 COM12 COM52 COM11 COM53 COM10 COM54 COM9 COM55 COM8 COM56 COM7 COM57 COM6 COM58 COM5 COM59 COM4 COM60 COM3 COM61 COM2 COM62 COM1 COM63 COM0 COM64 COM64 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM64 COM0 COM1 COM63 COM2 COM62 COM3 COM61 COM4 COM60 COM5 COM59 COM6 COM58 COM7 COM57 COM8 COM56 COM9 COM55 COM10 COM54 COM11 COM53 COM12 COM52 COM13 COM51 COM14 COM50 COM15 COM49 COM16 COM48 COM17 COM47 COM18 COM46 COM19 COM45 COM20 COM44 COM21 COM43 COM22 COM42 COM23 COM41 COM24 COM40 COM25 COM39 COM26 COM38 COM27 COM37 COM28 COM36 COM29 COM35 COM30 COM34 COM31 COM33 COM32 COM32 COM33 COM31 COM34 COM30 COM35 COM29 COM36 COM28 COM37 COM27 COM38 COM26 COM39 COM25 COM40 COM24 COM41 COM23 COM42 COM22 COM43 COM21 COM44 COM20 COM45 COM19 COM46 COM18 COM47 COM17 COM48 COM16 COM49 COM15 COM50 COM14 COM51 COM13 COM52 COM12 COM53 COM11 COM54 COM10 COM55 COM9 COM56 COM8 COM57 COM7 COM58 COM6 COM59 COM5 COM60 COM4 COM61 COM3 COM62 COM2 COM63 COM1 COM64 COM0
0
0
0
0
Page 0
IL[2:0]
IL[2:0]
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Start
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1
0
0
0
Page 8 59H 5AH 5BH 5CH 5DH 5EH 5FH
Column address
Display start line does not access 65th, 66th, 67th, 68th line
IMAGE lOCATION (IL[2:0]) + Partial display Area Width (19hex) <= Multiplexing Rate (40hex)
Normal Direction Reverse Direction S E G 0 S E G 95 S E G 1 S E G 94 S E G 2 S E G 93 S E G 3 S E G 92 S E G 4 S E G 91 S E G 5 S E G 90 S E G 6 S E G 89 S E G 89 S E G 6 S E G 90 S E G 5 S E G 91 S E G 4 S E G 92 S E G 3 S E G 93 S E G 2 S E G 94 S E G 1 S E G 95 S E G 0
SEG Output
36/62
Partial Display Area (25)
Start
Partial Display Area (24 +1)
STE2007
Display Data RAM (DDRAM)
5.3.3
17 Line partial display mode
Partial display area is composed of 17 Lines. Memory vs. Row Drivers Mapping is defined according to the following parameters: - - Multiplexing Value IL[2:0]
Figure 32. Partial display 17 lines
ICONMODE="1"
D a t D3 D2 D1 D0 a Page address D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM0 COM63 COM1 COM62 COM2 COM61 COM3 COM60 COM4 COM59 COM5 COM58 COM6 COM57 COM7 COM56 COM8 COM55 COM9 COM54 COM10 COM53 COM11 COM52 COM12 COM51 COM13 COM50 COM14 COM49 COM15 COM48 COM16 COM47 COM17 COM46 COM18 COM45 COM19 COM44 COM20 COM43 COM21 COM42 COM22 COM41 COM23 COM40 COM24 COM39 COM25 COM38 COM26 COM37 COM27 COM36 COM28 COM35 COM29 COM34 COM30 COM33 COM31 COM32 COM32 COM31 COM33 COM30 COM34 COM29 COM35 COM28 COM36 COM27 COM37 COM26 COM38 COM25 COM39 COM24 COM40 COM23 COM41 COM22 COM42 COM21 COM43 COM20 COM44 COM19 COM45 COM18 COM46 COM17 COM47 COM16 COM48 COM15 COM49 COM14 COM50 COM13 COM51 COM12 COM52 COM11 COM53 COM10 COM54 COM9 COM55 COM8 COM56 COM7 COM57 COM6 COM58 COM5 COM59 COM4 COM60 COM3 COM61 COM2 COM62 COM1 COM63 COM0 COM64 COM64 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM64 COM0 COM1 COM63 COM2 COM62 COM3 COM61 COM4 COM60 COM5 COM59 COM6 COM58 COM7 COM57 COM8 COM56 COM9 COM55 COM10 COM54 COM11 COM53 COM12 COM52 COM13 COM51 COM14 COM50 COM15 COM49 COM16 COM48 COM17 COM47 COM18 COM46 COM19 COM45 COM20 COM44 COM21 COM43 COM22 COM42 COM23 COM41 COM24 COM40 COM25 COM39 COM26 COM38 COM27 COM37 COM28 COM36 COM29 COM35 COM30 COM34 COM31 COM33 COM32 COM32 COM33 COM31 COM34 COM30 COM35 COM29 COM36 COM28 COM37 COM27 COM38 COM26 COM39 COM25 COM40 COM24 COM41 COM23 COM42 COM22 COM43 COM21 COM44 COM20 COM45 COM19 COM46 COM18 COM47 COM17 COM48 COM16 COM49 COM15 COM50 COM14 COM51 COM13 COM52 COM12 COM53 COM11 COM54 COM10 COM55 COM9 COM56 COM8 COM57 COM7 COM58 COM6 COM59 COM5 COM60 COM4 COM61 COM3 COM62 COM2 COM63 COM1 COM64 COM0
0
0
0
0
Page 0
IL[2:0]
IL[2:0]
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
Partial Display Area (16+1)
Start
Start
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1
0
0
0
Page 8 59H 5AH 5BH 5CH 5DH 5EH 5FH
Column address
Display start line does not access 65th, 66th, 67th, 68th line
Image Location (1L[2:0]) + Partial display Area Width (11hex) <= Multiplexing Rate (40hex)
Normal Direction Reverse Direction S E G 0 S E G 95 S E G 1 S E G 94 S E G 2 S E G 93 S E G 3 S E G 92 S E G 4 S E G 91 S E G 5 S E G 90 S E G 6 S E G 89 S E G 89 S E G 6 S E G 90 S E G 5 S E G 91 S E G 4 S E G 92 S E G 3 S E G 93 S E G 2 S E G 94 S E G 1 S E G 95 S E G 0
SEG Output
Partial Display Area (17)
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Display Data RAM (DDRAM)
STE2007
5.3.4
9 Line partial display mode
Partial display area is composed of 9 Lines. Memory vs. Row Drivers Mapping is defined according to the following parameters: - - Multiplexing Value IL[2:0]
Figure 33. Partial display 9 lines
ICONMODE="1"
D Page address a t D3 D2 D1 D0 a D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 00H 01H 02H 03H 04H 05H 06H Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H COM Output Normal Reverse direction direction COM0 COM63 COM1 COM62 COM2 COM61 COM3 COM60 COM4 COM59 COM5 COM58 COM6 COM57 COM7 COM56 COM8 COM55 COM9 COM54 COM10 COM53 COM11 COM52 COM12 COM51 COM13 COM50 COM14 COM49 COM15 COM48 COM16 COM47 COM17 COM46 COM18 COM45 COM19 COM44 COM20 COM43 COM21 COM42 COM22 COM41 COM23 COM40 COM24 COM39 COM25 COM38 COM26 COM37 COM27 COM36 COM28 COM35 COM29 COM34 COM30 COM33 COM31 COM32 COM32 COM31 COM33 COM30 COM34 COM29 COM35 COM28 COM36 COM27 COM37 COM26 COM38 COM25 COM39 COM24 COM40 COM23 COM41 COM22 COM42 COM21 COM43 COM20 COM44 COM19 COM45 COM18 COM46 COM17 COM47 COM16 COM48 COM15 COM49 COM14 COM50 COM13 COM51 COM12 COM52 COM11 COM53 COM10 COM54 COM9 COM55 COM8 COM56 COM7 COM57 COM6 COM58 COM5 COM59 COM4 COM60 COM3 COM61 COM2 COM62 COM1 COM63 COM0 COM64 COM64 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
ICONMODE="0"
COM Output Normal Reverse direction direction COM64 COM0 COM1 COM63 COM2 COM62 COM3 COM61 COM4 COM60 COM5 COM59 COM6 COM58 COM7 COM57 COM8 COM56 COM9 COM55 COM10 COM54 COM11 COM53 COM12 COM52 COM13 COM51 COM14 COM50 COM15 COM49 COM16 COM48 COM17 COM47 COM18 COM46 COM19 COM45 COM20 COM44 COM21 COM43 COM22 COM42 COM23 COM41 COM24 COM40 COM25 COM39 COM26 COM38 COM27 COM37 COM28 COM36 COM29 COM35 COM30 COM34 COM31 COM33 COM32 COM32 COM33 COM31 COM34 COM30 COM35 COM29 COM36 COM28 COM37 COM27 COM38 COM26 COM39 COM25 COM40 COM24 COM41 COM23 COM42 COM22 COM43 COM21 COM44 COM20 COM45 COM19 COM46 COM18 COM47 COM17 COM48 COM16 COM49 COM15 COM50 COM14 COM51 COM13 COM52 COM12 COM53 COM11 COM54 COM10 COM55 COM9 COM56 COM8 COM57 COM7 COM58 COM6 COM59 COM5 COM60 COM4 COM61 COM3 COM62 COM2 COM63 COM1 COM64 COM0
0
0
0
0
Page 0
IL[2:0]
IL[2:0]
0
0
0
1
Page 1
0
0
1
0
Page 2
Partial Display Area (8+1)
0
0
1
1
Page 3
Start
Start
0
1
0
0
Page 4
0
1
0
1
Page 5
0
1
1
0
Page 6
0
1
1
1
Page 7
1
0
0
0
Page 8 59H 5AH 5BH 5CH 5DH 5EH 5FH
Column address
Display start line does not access 65th, 66th, 67th, 68th line
Image Location (1L[2:0]) + Partial display Area Width (11hex) <= Multiplexing Rate (40hex)
Normal Direction Reverse Direction S E G 0 S E G 95 S E G 1 S E G 94 S E G 2 S E G 93 S E G 3 S E G 92 S E G 4 S E G 91 S E G 5 S E G 90 S E G 6 S E G 89 S E G 89 S E G 6 S E G 90 S E G 5 S E G 91 S E G 4 S E G 92 S E G 3 S E G 93 S E G 2 S E G 94 S E G 1 S E G 95 S E G 0
SEG Output
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Partial Display Area (9)
STE2007
Display Data RAM (DDRAM)
5.4
Table 17.
Command parameters default configuration
Command parameters default configuration
Status After Power On MCU TxData-mode Power Saver Mode All Pixel On OFF OFF Random 0hex 0hex 0hex Normal Normal 4hex 90hex Booster OFF 0hex 5x 1/10 0ppm Frame Inv. 1/68 80Hz 0hex Disabled After HW Reset MCU TxData-mode Power Saver Mode All Pixel On OFF OFF No change 0hex 0hex 0hex Normal Normal 4hex 90hex Booster OFF 0hex 5x 1/10 0ppm Frame Inv. 1/68 80Hz 0hex Disabled After SW Reset MCU TxData-mode Power Saver Mode All Pixel On OFF OFF No change 0hex 0hex 0hex Normal Normal 4hex 90hex Booster OFF 0hex 5x 1/10 0ppm Frame Inv. 1/68 80Hz 0hex Disabled IDA/IDB Pads Description
Driver status Power saver mode Display mode Inversion Display Frame memory Page address Columns address Display start line Segment drivers direction Common drivers direction VOR - Voltage range Electronic volume Power control register ID byte Charge pump Bias Ratio VLCD Temperature Comp. N-Line inversion Multiplexing rate Refresh rate Image location Icon mode
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Instruction setups
STE2007
6
6.1
Instruction setups
Initialization (power on sequence)
Power ON
Reset status
V0-Voltage Range (**H) Electronic volume (**H) Power saver OFF (Display all points OFF (A4H))
Power control set (2FH)
6.2
Display data writing sequence
Page address set (B*H) Column address set Upper 3-bit address (1*H) Column address set Lower 4-bit address (0*H)
Display data write This command is needed only at 1st time after initialization.
Display ON (AFH)
6.3
Power off
Optional Status !RES Pin="Low Level" min.20ms
VDD - GND Power OFF VDDI - GND Power OFF
Power Saver Status or Booster OFF Status !RES Pin="Low Level" min. 0ms
VDD - GND Power OFF VDDI - GND Power OFF
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Power on/power off timing sequence
7
Power on/power off timing sequence
Figure 34 shows the timing diagram for power on/power down sequences.
Figure 34. Timing for phone's power on sequence when VDD,VDDCP Up before VDDI
tp1 > 0 tp1 > 0
VDDI VDD
tpi >0s tpi >0s
Inputs Outputs
High-Z tcs >0s tcs >0s High-Z
!CS
tPWROFF1 >0 ms tPWROFF2 >20ms tp2 >0s
!RES
trs = max. 5s
INTERNAL RESET
Reset State
Trs = max. 5s
Reset State
XCS,SDAIN,XRES can become "High" simultaneously with VDDI (tcs>0,tpi>0;tp2>0). trs= max 5000ns (Internal Reset Time- see AC Characteristics Paragraph) tPWROFF1>0ms must be considered when driver is in Power Saver or Booster OFF status tPWROFF2>20ms must be considered when driver is in Normal Working Condition VDDI, VDD and VDD_CP can come up/go down in any sequence VDDI can be Up with VDD, VDDCP down and viceversa. If only one supply rail is up, the driver is forced in reset state. If VDD is high after VDDI all timing referred to VDDI must be referred to VDD (Fig. 24) Figure 35. Timing for phone's power on sequence when VDDI Up before VDD
tp1 < 0 tp1 < 0
VDDI VDD
tpi >0s tpi >0s
SDAIN SDAOUT
High-Z tcs >0s tcs >0s High-Z
!CS
tPWROFF1 >0 ms tPWROFF2 >20ms tp2 >0s
!RES
trs = max. 5s
INTERNAL RESET
Reset State
Trs = max. 5s
Reset State
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Power on/power off timing sequence
STE2007
Table 18.
Instruction Set
Code Function (D/C) D7 D6 0 0 0 0 0 0 1 D5 1 1 1 1 0 0 D4 0 0 0 1 1 0 * D3 1 0 0 D2 1 1 1 D1 1 1 0 D0 Hex 0 1 0 1 0 1 AE LCD display AF 0: OFF, 1: ON A6 LCD display A7 0: normal, 1: reverse A4 LCD display A5 0: normal display, 1: all points ON Sets the DDRAM page address
Command
Display ON/OFF Display normal/reverse Display all points ON/OFF Page address set Column address set upper 3-bit address Column address set lower 4-bit address Display start line address set Segment driver direction
0 0 0 0 0 0 0
1 1 1 1 0 0 0
address address
Sets the DDRAM column address address address Sets the DDRAM display start line address 0 1 Sets the correspondence between A0 the DDRAM column address and A1 the SEG driver output. 0:Normal, 1: reverse Sets the correspondence between the DDRAM line address and the COM driver output. 0: normal, 1: reverse Writes to the DDRAM 0 1 1 DB Identification byte Sets the on-chip power supply circuit operating mode Sets the electronic volume value Sets the electronic volume value Compound command of Display OFF and Display-all-points-ON E2 Internal reset E3 Non-operation E1 Sets the VLCD 0 0 Termal Compensation 0 * * * * * 0 0 1 VOP[7:0] 1 1 0 0 Thermal Comp 0 38 SET VLCD Slope in temperature
0
1
0
1
0
0
0
0
Common driver direction select
0
1
1
0
0
0 1
*
*
*
Display data write Self Test/Identification data reading Power control set VO-Range Electronic volume Power saver Reset NOP VOP
1 0 0 0 0 - 0 0 0 1 0 0 1 - 1 1 1 1 0 0 0 - 1 1 1 0 1 1 0 - 1 1 1
Write data 1 0 0 1 1 0
Operating mode VO-Range
Electronic volume value - 0 0 0 - 0 0 0 - 0 0 0 - 1 1 0 - 0 1 1
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STE2007
Power on/power off timing sequence
Table 18.
Instruction Set (continued)
Code Function (D/C) D7 0 0 * 1 * 0 1 * 1 1 * 1 1 * 1 1 1 1 1 1 1 D6 0 * 1 * 0 0 * 1 0 * 1 0 * 0 0 0 1 1 1 1 D5 1 * 1 * 1 1 F1 0 1 * 1 1 * 1 1 1 1 1 1 1 1 0 * 1 0 * 0 0 0 1 1 1 1 D4 1 * 0 * 1 0 D3 1 * 1 * 0 1 D2 1 * 1 * D1 0 D0 Hex 1 3D Sets the Charge Pump Mux Factor
Command
Charge Pump 0 0 Refresh Rate 0 Bias ratio N-line Inversion 0 Number of Lines Image Location 0 Icon Mode 0 0 STM TEST MODE1 0 STM TEST MODE2 STM TEST MODE3 STM TEST MODE4 STM TEST MODE5 STM TEST MODE6 STM TEST MODE7 STM TEST MODE8 0 0 0 0 0 0 0 * 1 1 1 1 1 1 1 * 0 0 0 1 1 1 1 * 1 1 0 0 0 0 0 0
Charge Pump 1 1 EF Sets the Display Refresh Frequency
Refersh Rate
Bias Ratio 1 0 1 AD
Sets the VLCD
N-Line Inversion 0 1 Mux Rate 1 0 IL[2:0] 0 0 * 1 1 0 1 0 1 0 Ico n 1 * 0 1 0 1 0 0 1 A9 Reserved for STM (STM Test Mode) AA AB A8 FF FC FE FD Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) Reserved for STM (STM Test Mode) 0 AC SET Initial Row on Display
* = Disabled bits.
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Commands
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8
8.1
Table 19.
(D/C) 0 0
Commands
Display on/off
This command turns the display ON and OFF Display on/ofF
D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 1 HEX AE AF Setting Display OFF Display ON
When the Display OFF command is executed in the Display all points ON mode, Power saver mode is entered. See the section on the Power saver for details.
8.2
Display normal/reverse
This command can reverse the lit and unlit without overwriting the contents of the DDRAM.
Table 20.
(D/C) 0 0 D7 1
Display normal/reverse
D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 1 HEX A6 A7 Setting Normal:DDRAM Data "H"=LCD ON voltage Reverse:DDRAM Data "L"=LCD ON voltage
8.3
Display all points on/off
This command makes it possible to force all display points ON regardless of the content of the DDRAM. Even when this is done, the DDRAM contents are maintained. This command takes priority over the Display normal/reverse command.
Table 21.
(D/C) 0 0 D7 1
Display all points ON/OFF
D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0 1 HEX A4 A5 Setting Normal Display Mode Display All Points ON
When the Display all points ON command is executed when in the Display OFF mode, Power saver mode is entered. See the section on the Power Saver for details.
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STE2007
Commands
8.4
Page address set
This command specifies the page address of the DDRAM. Specifying the page address and column address enables to access a desired bit of the DDRAM. After the last column address (5FH), page address is incremented by +1. After the very last address (column = 5FH, page = 8H), page address return to 0H.
Table 22.
(D/C) 0 0 0 0 0 D7 1
Page address set
D6 0 D5 1 D4 1 D3 0 0 0 D2 0 0 0 : 1 0 0 0 D1 0 0 1 D0 0 1 0 HEX B0 B1 B2 : B8 Setting 0H 1H 2H : 8H
8.5
Column address set
This command specifies the column address of the DDRAM. The column address is split into two sections (the upper 3-bits and lower 4-bits) when it is set. Each time the DDRAM is accessed, the column address automatically increments by +1, imaging it possible for the MCU to continuously access to the display data. After the last column address (5FH), column address returns to 00H.
Table 23.
(D/C) 0 D7 0
Column address set
D6 0 D5 0 D4 1 0 D3 * A3 D2 A6 A2 D1 A5 A1 D0 A4 A0 Setting Upper bit address Lower bit address
* Disabled bit
(D/C) 0 0 0 . . 0 0
A6 0 0 0
A5 0 0 0
A4 0 0 0
A3 0 0 0 . .
A2 0 0 0
A1 0 0 1
A0 0 1 0
Column address 00H 01H 02H
1 1
0 0
1 1
1 1
1 1
1 1
0 1
5EH 5FH
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Commands
STE2007
8.6
Display start line address set
This command is used to specify the display start line address of the DDRAM. If the display start line address is changed dynamically using this command, then screen scrolling, page swapping can be performed.
Table 24.
(D/C) 0 0 0 : 0 0 0 0 D7 0 0 0
Display start line address set
D6 1 1 1 D5 0 0 0 D4 0 0 0 D3 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 1 0 1 7E 7F D2 0 0 0 D1 0 0 1 D0 0 1 0 HEX 40 41 42 Setting 0H 1H 2H : 3EH 3FH
Display start line assress con be used in partial dispaly mode to relocate the partial display window on the screen. Display start line + Partial Display area with must be smaller or equal to the number of line selected.
8.7
Segment driver direction select
This command can reverse the correspondence between the DDRAM column address and the segment driver output.
Table 25.
(D/C) 0 0 D7 1
Segment driver direction select
D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 1 HEX A0 A1 Setting Normal Reverse
8.8
Common driver direction select
This command can reverse the correspondence between the DDRAM line address and the common driver output.
Table 26.
(D/C) 0 D7 1
Common driver direction select
D6 1 D5 0 D4 0 D3 0 1 D2 * * D1 * * D0 * * Setting Normal Reverse
* Disabled bit
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Commands
8.9
Display data write
This command writes 8-bit data to the specified DDRAM address. Since the column address is automatically incremented by +1 after each write, the MCU can continuously write multiple-word data.
Table 27.
(D/C) 1
Display data write
D7 D6 D5 D4 D3 D2 D1 D0
Write Data
8.10
Data reading from driver (Driver TxData-mode)
These commands set SDAOUT to Driver TxData-mode and enable to read the identification byte.
Table 28.
(D/C) 0 0 D7 1 0
ID Byte
D6 1 0 D5 0 IDB D4 1 IDA D3 1 0 D2 0 0 D1 1 0 D0 1 0 HEX DB Setting Reads ID byte Pad Default
8.11
Power Control Set
This command sets the on-chip power supply function ON/OFF.
Table 29.
(D/C) 0 0 0 0 0 0 0 0 D7 0
Power Control Set
D6 0 D5 1 D4 0 D3 1 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 HEX 28 29 2A 2B 2C 2D 2E 2F Booster : ON Voltage regulator : ON Voltage follower : ON Booster : OFF Voltage Regulator:OFF Voltage Follower : OFF Setting
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Commands
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8.12
VLCD set
The LCD Voltage VLCD at reference temperature (TA = 25C) can be set using the Voltage Range V0R, Electronic Volume EV and VOP registers content according to the following formula: VLCD (T=TA) = ( V0P[7:0] + EV[4:0] - 16 + 32 * V0R[2:0]) * B + VLCDMIN with the following values:
Symbol B VLCDMIN TA Value 0.04 3 25 Unit V V C Room Temperature Note Single Voltage Step
For information on VLCD thermal compensation see PAR. 8.18 . Figure 36.
Vout 13.20V EV[3:0]
12h 10h 11h 1Fh
B
00h
VOP[7:0]*B+V-OR
3V
00h
FFh
Figure 37.
V0R[2:0] EV[4:0] DAC Step: 40mV Range 3V-13.20V Thermal Compensation VOUT
8.12.1
V0R - Voltage Range Set
This command sets a value of the Voltage Range.
Table 30.
(D/C) 0
V0R - Voltage Range
D7 0 D6 0 D5 1 D4 0 D3 0 D2 D1 D0 Setting Command Identifier + Data Field
V0R - Voltage Range
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STE2007
Commands
Table 31.
(D/C) 0 0 0 0 0 0 0 0 D7 0
V0R
D6 0 D5 1 D4 0 D3 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 HEX 20 21 22 23 24 25 26 27 V0R Value 0 1 2 3 4 5 6 7 32 * V0R * B + VLCDMIN 3.00 V 4.28 V 5.56 V 6.84 V 8.12 V (Default) 9.40 V 10.68 V 11.96 V
8.12.2
VOP set
Contrast Setting Adjustment .
Table 32.
(D/C) 0 0 D7 1
VOP Set
D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 HEX E1 Function Command Identifier Data Field
VOP7 VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0
Table 33.
VOP
HEX 00 01 02 : 7F 80 81 : FD FE FF VOP Adjustment 0 Step (Default) +1 Step +2 Step : +127 Step 0 Step -1 Step : -125 Step -126 Step -127 Step
VOP7 VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 0 0 0 : 0 1 1 : 1 1 1 0 0 0 : 1 0 0 : 1 1 1 0 0 0 : 1 0 0 : 1 1 1 0 0 0 : 1 0 0 : 1 1 1 0 0 0 : 1 0 0 : 1 1 1 0 0 0 : 1 0 0 : 1 1 1 0 0 1 : 1 0 0 : 0 1 1 0 1 0 : 1 0 1 : 1 0 1
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Commands
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8.12.3
Electronic volume
This command sets a value of electronic volume EV for the VLCD voltage regulator, to adjust the contrast of LCD panel display (End User).
Table 34.
(D/C) 0
Electronic volume
D7 1 D6 0 D5 0 D4 D3 D2 D1 D0 Setting Command Identifier + Data Field
Electronic Volume Value
Table 35.
(D/C) 0 0 0 : 0 : 0 0 D7 1
EV
D6 0 D5 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 : 1 0 0 : 1 1 1 1 1 1 1 1 0 1 0 0 D1 0 0 1 D0 0 1 0 Hex 80 81 82 : 90 : 9E 9F EV Value 0 Step 1 Step 2 Step : 16 Step (Default) : 30 Step 31 Step high : : VLCD voltage low
8.13
Power saver mode
If the display all points ON command is executed when the display is in display OFF mode, power saver mode is entered. This mode stops every operation of the LCD display system. Figure 38. Power saver mode
Power saver (Display OFF & Display all points ON
Command
Power saver mode Powersaver OFF (Display all points OFF)
Effect
Power saver mode canceled
The internal states in power saver mode are as follows: - - - - The oscillation circuit is stopped The LCD power supply circuit is stopped The LCD driver circuit is stopped and segment/common driver outputs to the Vss level The display data and operation mode before execution of the Power saver are held, and the MCU can access to the DDRAM and internal registers.
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Commands
8.14
Reset
When this command is issued, the driver is initialized.This command doesn't change DDRAM content.
Table 36.
(D/C) 0 D7 1
Reset
D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 HEX E2 Function Command Identifier
8.15
Table 37.
(D/C) 0 D7 1
NOP
Non-operation command. NOP
D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 HEX E3 Function Command Identifier
8.16
Image Location
Image Location Command
Table 38.
(D/C) 0 0
Image Location
D7 1 * D6 0 * D5 1 * D4 0 * D3 1 * D2 1 IL2 D1 0 IL1 D0 0 IL0 HEX AC Function Command Identifier Data Field
Table 39.
IL2 0 0 0 0 1 1 1 1
Image Location
IL1 0 0 1 1 0 0 1 1 IL0 0 1 0 1 0 1 0 1 Function 0 Lines 8 Lines 16 Lines 24 Lines 32 Lines 48 Lines 56 Lines 64 Lines
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Commands
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8.17
Table 40.
(D/C) 0
Bias Ratio
It is possible to select different Bias Ratio. Bias Ratio
D7 0 D6 0 D5 1 D4 1 D3 0 D2 BR2 D1 BR1 D0 BR0 Function Command Identifier + Data Field
Table 41.
BR2 0 0 0 0 1 1 1 1
BIAS Ratio
BR1 0 0 1 1 0 0 1 1 BR0 0 1 0 1 0 1 0 1 Function Bias Ratio =1/10 - 81 Lines Bias Ratio = 1/9 - 65 Lines Bias Ratio =1/8 - 49 Lines Bias Ratio = 1/7 - 33 Lines Bias Ratio =1/6 - 25 Lines Bias Ratio = 1/5 - 17 Lines Bias Ratio =1/4 - 9 Lines Not Used
Figure 39. Bias levels Generator
BR=000
VLCD
BR=001
VLCD R 9 *VLCD 10 8 *VLCD 9 R 8 *VLCD 10 7 *VLCD 9 5R 2 *VLCD 10 2 *VLCD 9 R 1 *VLCD 10 1 *VLCD 9 R
BR=010
VLCD
BR=011
VLCD R 7 *VLCD 8 6 *VLCD 7 R 6 *VLCD 8 5 *VLCD 7 3R 2 *VLCD 8 2 *VLCD 7 R 1 *VLCD 8 1 *VLCD 7 R
R
R
R
R
6R
4R
R
R
R
R
VSS
VSS
VSS
VSS
BR=100
VLCD
BR=101
VLCD R 5 *VLCD 6 4 *VLCD 5 R 4 *VLCD 6 3 *VLCD 5 1R 2 *VLCD 6 2 *VLCD 5 R 1 *VLCD 6 1 *VLCD 5 R
BR=110
VLCD
R
R 3 *VLCD 4 R 2 *VLCD 4 4R 2 *VLCD 4 R 1 *VLCD 4 R
R
2R
R
R
VSS
VSS
VSS
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Commands
8.18
Temperature Compensation
Its is possible to select different VLCD temperature compensation Coefficients.
Table 42.
(D/C) 0 0
VLCD Temperature Compensation
D7 0 * D6 0 * D5 1 * D4 1 * D3 1 * D2 0 D1 0 Thermal Compensation TC D0 0 HEX 38 Function Command Identifier Data Field
Temperature Compensation Formula: VLCD(T) = VLCD(TA) * [1 + (T(C) - TA) * TC] TC = Temperature Compensation Coefficients T(C) = Temperature VLCD(TA) = LCD Voltage at TA Temperature (Room Temperature) Table 43.
TC2 0 0 0 0 1 1 1 1
TC
TC0 0 1 0 1 0 1 0 1 TC Value TC= 0 PPM TC= -300 PPM TC= -600 PPM TC= -900 PPM TC= -1070 PPM TC= -1200 PPM TC= -1500 PPM TC= -1800 PPM
TC1 0 0 1 1 0 0 1 1
8.19
Charge Pump Multiplication Factor
It is possible to select different Charge Pump Multiplication Factors.
Table 44.
(D/C) 0 0
Charge Pump Setting
D7 0 * D6 0 * D5 1 * D4 1 * D3 1 * D2 1 * D1 0 CP1 D0 1 CP0 HEX 3D Function Command Identifier Data Field
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Table 45.
CP1 0 0 1 1
Charge Pump Multiplication Factor
CP0 0 1 0 1 Function 5x 4x 3x Not Used
8.20
Table 46.
(D/C) 0 0 D7 1 *
Refresh Rate
It is possible to select different Refresh Rate. Refresh rate setting
D6 1 * D5 1 * D4 0 * D3 1 * D2 1 * D1 1 RR1 D0 1 RR0 HEX EF Function Command Identifier Data Field
Table 47.
RR1 0 0 1 1
Refresh Rate
RR0 0 1 0 1 Function 80 Hz 75 Hz 70 Hz 65 hz
8.21
Icon mode
Icon Mode - - 0: Icon Mode Disabled 1: Icon Mode Enabled
Table 48.
(D/C) 0
Icon Mode
D7 1 D6 1 D5 1 D4 1 D3 1 D2 0 D1 0 D0 ICON Function Command Identifier
8.22
Table 49.
(D/C) 0 0 D7 1 *
N- Line inversion
N-line Inversion Function. N-Line Inversion
D6 0 * D5 1 F1 D4 0 NL4 D3 1 NL3 D2 1 NL2 D1 0 NL1 D0 1 NL0 HEX AD Function Command Identifier Data Field
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Pad coordinates
Table 50.
F1 * 0 1 * * : * NL4 0 * * 0 0 : 1
N-Line
NL3 0 * * 0 0 : 1 NL2 0 * * 0 0 : 1 NL1 0 * * 0 1 : 1 NL0 0 * * 1 0 : 1 Function N-line inversion disabled (default) XOR function disabled XOR function enabled N-line inversion enabled N-line inversion enabled : N-line inversion enabled 2 3 : 32 N row
The XOR function defines the polarity as the result of the logical XOR between the N-Line and the frame polarity.
8.23
Table 51.
(D/C) 0
Number of lines
Multiplexing Rate setting command. Number of lines
D7 1 D6 1 D5 0 D4 1 D3 0 D2 M2 D1 M1 D0 M0 Function Command Identifier + Data Field
Table 52.
M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1
Multiplexing rate
M0 0 1 0 1 0 1 0 1 Function 68 Lines (Default) 65 Lines 49 Lines 33 Lines 33 Lines Partial Display 25 Lines Partial Display 17 Lines Partial Display 9 Lines Partial Display
9
Pad coordinates
See Table 53: Pad coordinates and Table 55: Alignment marks coordinates.
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Pad coordinates
STE2007
Table 53.
Name R16 R14 R12 R10 R8 R6 R4 R2 R0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24
Pad coordinates
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 X (m) -2632.5 -2587.5 -2542.5 -2497.5 -2452.5 -2407.5 -2362.5 -2317.5 -2272.5 -2227.5 -2182.5 -2137.5 -2092.5 -2047.5 -2002.5 -1957.5 -1912.5 -1867.5 -1822.5 -1777.5 -1732.5 -1687.5 -1642.5 -1597.5 -1552.5 -1507.5 -1462.5 -1417.5 -1372.5 -1327.5 -1282.5 -1237.5 -1192.5 -1147.5 Y(m) -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 Name C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 Pad 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 X (m) -1102.5 -1057.5 -1012.5 -967.5 -922.5 -877.5 -832.5 -787.5 -742.5 -697.5 -652.5 -607.5 -562.5 -517.5 -472.5 -427.5 -382.5 -337.5 -292.5 -247.5 -202.5 -157.5 -112.5 112.5 157.5 202.5 247.5 292.5 337.5 382.5 427.5 472.5 517.5 562.5 Y(m) -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35
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Pad coordinates
Table 53.
Name C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93
Pad coordinates (continued)
Pad 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 X (m) 607.5 652.5 697.5 742.5 787.5 832.5 877.5 922.5 967.5 1012.5 1057.5 1102.5 1147.5 1192.5 1237.5 1282.5 1327.5 1372.5 1417.5 1462.5 1507.5 1552.5 1597.5 1642.5 1687.5 1732.5 1777.5 1822.5 1867.5 1912.5 1957.5 2002.5 2047.5 2092.5 2137.5 Y(m) -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 Name C94 C95 R1 R3 R5 R7 R9 R11 R13 R15 R17 R19 R21 R23 R25 R27 R29 R31 R33 R35 R37 R39 R41 R43 R45 R47 R49 R51 R53 R55 R57 R59 R61 R63 R65 Pad 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 X (m) 2182.5 2227.5 2272.5 2317.5 2362.5 2407.5 2452.4 2497.5 2542.5 2587.5 2632.5 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2831.85 2632.5 2587.5 2542.0 Y(m) -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -514.35 -450.0 -405.0 -360.0 -315.0 -270.0 -225.0 -180.0 -135.0 -90.0 -45.0 0.0 45.0 90.0 135.0 180.0 225.0 270.0 315.0 360.0 405.0 450.0 514.35 514.35 514.35
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Pad coordinates
STE2007
Table 53.
Name R67 TEST3 TEST4 VSS_AUX VSS_AUX VSS_AUX VSS_AUX N_RES N_CS T2 T1 T0 VSS VSS VSS VSS_LCD VSS_LCD VSS_LCD VSS_CP VSS_CP VSS_CP DC SDAOUT SDIN SDOUT SCLK
Pad coordinates (continued)
Pad 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 X (m) 2497.5 2376.0 2304.0 1944.0 1872.0 1800.0 1728.0 1584.0 1512.0 1368.0 1296.0 1224.0 1152.0 1080.0 1008.0 936.0 864.0 792.0 720.0 648.0 576.0 432.0 360.0 288.0 216.0 144.0 72.0 -72.0 -144.0 -216.0 -288.0 -360.0 -432.0 -504.0 -576.0 Y(m) 514.35 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 Name VDDI VDDI VDDI VDDI VDDI VDDI VDD VDD VDD VDD VDD VDD VDD_CP VDD_CP VLCD_SNS VLCD VLCD VLCD VLCD TEST4 TEST5 R66 R64 R62 R60 R58 R56 R54 R52 R50 R48 R46 R44 R42 R40 Pad 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 X (m) -720.0 -792.0 -864.0 -936.0 -1008.0 -1080.0 -1224.0 -1296.0 -1368.0 -1440.0 -1512.0 -1584.0 -1656.0 -1728.0 -1872.0 -1944.0 -2016.0 -2088.0 -2160.0 -2304.0 -2376.0 -2497.5 -2542.5 -2587.5 -2632.5 -2831.85 -2831.85 -2831.85 -2831.85 -2831.85 -2831.85 -2831.85 -2831.85 -2831.85 -2831.85 Y(m) 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 517.5 514.35 514.35 514.35 514.35 450.0 405.0 360.0 315.0 270.0 225.0 180.0 135.0 90.0 45.0
VREF_BUFF VSS_AUX SEL1 SEL0 SA1 SA0 IDB IDA OSC_IN
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Pad coordinates
Table 53.
Name R38 R36 R34 R32 R30 R28
Pad coordinates (continued)
Pad 209 210 211 212 213 214 X (m) -2831.85 -2831.85 -2831.85 -2831.85 -2831.85 -2831.85 Y(m) 0.0 -45.0 -90.0 -135.0 -180.0 -225.0 Name R26 R24 R22 R20 R18 Pad 215 216 217 218 219 X (m) -2831.85 -2831.85 -2831.85 -2831.85 -2831.85 Y(m) -270.0 -315.0 -360.0 -405.0 -450.0
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Chip mechanical drawing
STE2007
10
Chip mechanical drawing
Table 54. Mechanical dimensions
Parameter Wafer Thickness Die Size (X x Y) Bumps Size on Columns and Segments Side Pad Size on Columns and Segments Side Bumps Pitch on Columns and Segments Side Bumps Size on Interfaces Side Pad Size on Interfaces Side Bumps Pitch on Interfaces Side Spacing between Bumps Dimensions 500m 5.92 mm x 1.29 mm 28m X 89 m X 15 35m X 96m 45m 55m X 73m X 15 64 m X 82 m 72m 17m
Table 55.
Alignment marks coordinates
MARKS X -2834.55 2834.55 -2834.55 2834.55 2205.0 Y 517.05 517.05 -517.05 -517.05 517.05
Mark1 Mark2 Mark3 Mark4 Mark5
Figure 40. Alignment marks dimensions
35 m 85 m
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STE2007
Ordering information
11
Ordering information
Table 56. Order codes
Part number STE2007DIE2 Type Bumped Dice on Waffle Pack
12
Revision history
Table 57.
Date 09-Nov-2005 13-Mar-2006
Document revision history
Revision 1 2 Initial release. Adjustments in Abs Max ratings regarding ESD in Table 7. Adjustments on DC & AC charactersitics (VLCD, I(VDDI) in Table 8 & FFRAME in Table 9) Reviewed operating temperature range in Chapter 3: Electrical characteristics. Changes
12-Dec-2006
3
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STE2007
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